IBM and Lam Research have announced a five-year collaboration to develop processes for sub-1nm logic chips, focusing on integrating Lam's Aether dry resist technology with high-NA EUV lithography at IBM's Albany research facility.
The partnership aims to validate full process flows for advanced device architectures like nanosheet transistors and backside power delivery. A key goal is proving the dry resist process can reliably transfer high-NA EUV patterns into device layers at production yield, a necessary step for future chip scaling.
The main topics covered are the technical collaboration on next-generation chip fabrication, the advantages of the dry resist process over wet chemistry for reducing defects at tiny scales, and the specific device architectures and tools involved.
IBM and Lam's new partnership paves the way toward sub-1nm logic using High-NA EUV — Albany lab to pioneer dry resist process integration
The collaboration targets high-NA EUV dry resist process integration at IBM's Albany research facility.
Get Tom's Hardware's best news and in-depth reviews, straight to your inbox.
You are now subscribed
Your newsletter sign-up was successful
IBM and Lam Research have announced a five-year research collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using high-NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's NY Creates Albany NanoTech Complex in New York, with Lam's Aether dry resist technology at the center of the effort alongside its Kiyo and Akara etch platforms and Striker and ALTUS Halo deposition systems.
The two companies have collaborated for over a decade on 7nm process development, nanosheet transistor architecture, and early EUV process integration. Notably, IBM unveiled what it described as the world's first 2nm node chip in 2021, marking a significant milestone in the ongoing partnership.
Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.
Article continues belowAether and high-NA EUV
Standard EUV lithography utilizes chemically amplified resists, which are spin-coated onto wafers and developed using wet chemistry. That approach, however, has a fundamental problem at the geometries high-NA EUV scanners are designed to print: stochastic noise. This is a statistical variation in photon absorption per unit area, which drives defect rates up as features shrink.
Aether’s process, however, sidesteps wet chemistry entirely by depositing the resist via vapor-phase precursors and developing it using plasma-based dry processes. According to Lam, its metal-organic compounds absorb three to five times more EUV light than conventional carbon-based resist materials, reducing the exposure dose required per wafer pass and keeping single-print patterning viable at nodes where wet-process alternatives would require more expensive multi-patterning.
Fewer process steps between exposure and etch also reduce the number of points at which pattern fidelity can degrade, which is a compounding advantage as geometries continue to tighten. The renewed collaboration between IBM and Lam is specifically focused on proving that Aether can get high-NA EUV patterns reliably transferred into real device layers at production yield. Ultimately, that’s what needs to be done before sub-1nm processes can credibly move toward a production fab.
Nanosheet transistors, which stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint, are one of the primary device architectures the teams will be validating. IBM’s press release also confirms work on nanostack devices and backside power delivery, which routes power connections through the back of the wafer rather than the front, freeing up front-side metal layers for signal routing and reducing the resistance losses that compound at high transistor densities.
Three deals in 14 months
The IBM announcement marks the third significant Aether-related move Lam has made since January last year. The company confirmed that month that Aether had been selected by an unnamed leading memory manufacturer as the production tool of record for its most advanced DRAM processes. Then, in September, Lam signed a cross-licensing and collaboration agreement with JSR Corporation and its subsidiary Inpria, integrating JSR's metal oxide resists and patterning materials with Lam's etch, deposition, and dry resist capabilities for high-NA EUV.
Across 14 months, Lam has moved from production adoption in memory to a materials supply chain partnership for high-NA EUV patterning to a five-year logic research commitment with IBM, assembling a dry resist ecosystem ahead of wider high-NA EUV adoption. ASML began shipping its first high-NA EUV systems in 2023, and as those tools move toward broader foundry adoption, the choice of resist process will become one of the more consequential materials chipmakers face. JSR and Inpria's existing metal oxide resist expertise is a direct complement to Aether's vapor deposition approach, giving Lam coverage across both dry resist and metal oxide patterning materials heading into sub-1nm.
Lam isn’t the only equipment company circling high-NA EUV. Applied Materials has its own patterning materials and process integration capabilities, and ASML's dominant position in lithography gives it natural leverage over how the resist ecosystem develops around its tools. Lam's partnerships with IBM and JSR/Inpria are, at least in part, an effort to establish dry resist as the default process integration path before tooling decisions are embedded within foundries.
IBM's research complex
IBM Research's Albany NanoTech Complex is a process development facility, not a production fab, so the output of this collaboration will be validated process flows and materials knowledge that commercial foundries can adopt.
This follows the same model as the companies' prior work on 7nm and nanosheet, with the research that was demonstrated at Albany eventually feeding into production processes at TSMC and others. Sub-1nm process work starting in 2026 is therefore unlikely to reach volume manufacturing before the early 2030s.
The collaboration also presents a huge opportunity for Lam. If it’s able to establish Aether as the validated dry resist solution for high-NA EUV logic, it stands to add a significant new revenue category on top of the etch and deposition tools it already sells to nearly every advanced chipmaker.
A five-year commitment with IBM builds process familiarity and customer confidence well before foundries are making resist process decisions for their sub-1nm nodes. Lam's commercial customers — TSMC, Samsung, Intel, and others — are the ones who will ultimately adopt whatever process knowledge comes out of Albany as a result of this new research effort.
Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
Meridiano
